ISSN 2394-5125
 

Research Article 


ULTRA LOW POWER ROBUST 12T SRAM ARCHITECTURE BASED ON PARALLEL CROSS-COUPLING FEEDBACK

Dr.H.Kareemullah, Mr.C.Venkatnarayanan.

Abstract
Ultra-low power, low on-chip processing circuits are highly desirable for lightweight and wearable applications. Memory is an integral part of most of these systems and is also diminished as the scale of the system reduces. Low power and processing architecture at high speed is therefore a major concern. The durability of random static access memory cells (SRAM) is another critical factor. This paper provides a new standard memory cell based (SCM) twelve-transistor (12 T) circuit. In order to achieve high region performance and low energy usage, three gating transistors for each column of SRAM cells have been used. The three-stage read-out system eliminates reading delays as well as energy consumption. As compared to the previously published SCM circuit in a 65-nm CMOS technology, the read and write energy consumption per operation is reduced. In comparison to the previously published SCM circuit, read time and cell lay-out are also reduced . In comparison, the traditional T-architecture guarantees high data consistency and writes functionality with the proposed 12 T SRAM module.

Key words: SCM, twelve-transistor and SRAM cells


 
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How to Cite this Article
Pubmed Style

Dr.H.Kareemullah, Mr.C.Venkatnarayanan. ULTRA LOW POWER ROBUST 12T SRAM ARCHITECTURE BASED ON PARALLEL CROSS-COUPLING FEEDBACK. JCR. 2020; 7(19): 407-413. doi:10.31838/jcr.07.19.54


Web Style

Dr.H.Kareemullah, Mr.C.Venkatnarayanan. ULTRA LOW POWER ROBUST 12T SRAM ARCHITECTURE BASED ON PARALLEL CROSS-COUPLING FEEDBACK. http://www.jcreview.com/?mno=102154 [Access: September 14, 2020]. doi:10.31838/jcr.07.19.54


AMA (American Medical Association) Style

Dr.H.Kareemullah, Mr.C.Venkatnarayanan. ULTRA LOW POWER ROBUST 12T SRAM ARCHITECTURE BASED ON PARALLEL CROSS-COUPLING FEEDBACK. JCR. 2020; 7(19): 407-413. doi:10.31838/jcr.07.19.54



Vancouver/ICMJE Style

Dr.H.Kareemullah, Mr.C.Venkatnarayanan. ULTRA LOW POWER ROBUST 12T SRAM ARCHITECTURE BASED ON PARALLEL CROSS-COUPLING FEEDBACK. JCR. (2020), [cited September 14, 2020]; 7(19): 407-413. doi:10.31838/jcr.07.19.54



Harvard Style

Dr.H.Kareemullah, Mr.C.Venkatnarayanan (2020) ULTRA LOW POWER ROBUST 12T SRAM ARCHITECTURE BASED ON PARALLEL CROSS-COUPLING FEEDBACK. JCR, 7 (19), 407-413. doi:10.31838/jcr.07.19.54



Turabian Style

Dr.H.Kareemullah, Mr.C.Venkatnarayanan. 2020. ULTRA LOW POWER ROBUST 12T SRAM ARCHITECTURE BASED ON PARALLEL CROSS-COUPLING FEEDBACK. Journal of Critical Reviews, 7 (19), 407-413. doi:10.31838/jcr.07.19.54



Chicago Style

Dr.H.Kareemullah, Mr.C.Venkatnarayanan. "ULTRA LOW POWER ROBUST 12T SRAM ARCHITECTURE BASED ON PARALLEL CROSS-COUPLING FEEDBACK." Journal of Critical Reviews 7 (2020), 407-413. doi:10.31838/jcr.07.19.54



MLA (The Modern Language Association) Style

Dr.H.Kareemullah, Mr.C.Venkatnarayanan. "ULTRA LOW POWER ROBUST 12T SRAM ARCHITECTURE BASED ON PARALLEL CROSS-COUPLING FEEDBACK." Journal of Critical Reviews 7.19 (2020), 407-413. Print. doi:10.31838/jcr.07.19.54



APA (American Psychological Association) Style

Dr.H.Kareemullah, Mr.C.Venkatnarayanan (2020) ULTRA LOW POWER ROBUST 12T SRAM ARCHITECTURE BASED ON PARALLEL CROSS-COUPLING FEEDBACK. Journal of Critical Reviews, 7 (19), 407-413. doi:10.31838/jcr.07.19.54