ISSN 2394-5125
 

Research Article 


LOW POWER INPUT CLOCKED LATCH DESIGN BASED ON A SIGNAL FEED THROUGH USING FINFET TECHNOLOGY

Naresh Bopparathi, Dr. P. Kalpana Devi.

Abstract
Flip-flops are the electronic devices which are most commonly used to store or transfer the data.
These devices are mainly used to change the state of input signal. The circuit mainly takes two inputs, data
signal and clock signal respectively. These inputs have different pulse widths. Though these devices are very
essential in the field of circuit designing, the delay and power factors also needs to be considered. The main aim
of this is to design a low-power consuming flip-flop with less delay or transition time. Due to simple and clear
pulse-triggered circuitry and an improved clock input, the proposed design works very efficiently. Here, the
output data is given as one of the inputs to the circuit for the stability. The proposed design not only achieves
high speed and better power performance, it also eliminates the high discharging problem which can be
observed in the previous generation pulse triggered flip-flops. The proposed circuit can also make a
revolutionary change in various fields. Due to the optimization in the circuit, it has various applications like
registers, counters, memory elements, latches, etc. After verifying the post layout simulation output wave-forms
using fin-FET 18nm technology, the proposed circuit performs a way ahead of the previous generation flipflops. The existing single-phase triggered flip-flop using CMOS 90nm technology lacks in power and delay
whereas the proposed circuit achieves high speed of operation at low power.
The proposal not only improves power and delay factors, it also minimizes the circuit area as the proposed
model deals with fin-FET 18nm technology.

Key words: Flip-flop, Clock pulse, FinFET, Low Power, Delay, Pulse-triggered.


 
ARTICLE TOOLS
Abstract
PDF Fulltext
How to cite this articleHow to cite this article
Citation Tools
Related Records
 Articles by Naresh Bopparathi
Articles by Dr. P. Kalpana Devi
on Google
on Google Scholar


How to Cite this Article
Pubmed Style

Naresh Bopparathi, Dr. P. Kalpana Devi. LOW POWER INPUT CLOCKED LATCH DESIGN BASED ON A SIGNAL FEED THROUGH USING FINFET TECHNOLOGY. JCR. 2020; 7(19): 5593-5598. doi:10.31838/jcr.07.19.650


Web Style

Naresh Bopparathi, Dr. P. Kalpana Devi. LOW POWER INPUT CLOCKED LATCH DESIGN BASED ON A SIGNAL FEED THROUGH USING FINFET TECHNOLOGY. http://www.jcreview.com/?mno=133497 [Access: September 14, 2020]. doi:10.31838/jcr.07.19.650


AMA (American Medical Association) Style

Naresh Bopparathi, Dr. P. Kalpana Devi. LOW POWER INPUT CLOCKED LATCH DESIGN BASED ON A SIGNAL FEED THROUGH USING FINFET TECHNOLOGY. JCR. 2020; 7(19): 5593-5598. doi:10.31838/jcr.07.19.650



Vancouver/ICMJE Style

Naresh Bopparathi, Dr. P. Kalpana Devi. LOW POWER INPUT CLOCKED LATCH DESIGN BASED ON A SIGNAL FEED THROUGH USING FINFET TECHNOLOGY. JCR. (2020), [cited September 14, 2020]; 7(19): 5593-5598. doi:10.31838/jcr.07.19.650



Harvard Style

Naresh Bopparathi, Dr. P. Kalpana Devi (2020) LOW POWER INPUT CLOCKED LATCH DESIGN BASED ON A SIGNAL FEED THROUGH USING FINFET TECHNOLOGY. JCR, 7 (19), 5593-5598. doi:10.31838/jcr.07.19.650



Turabian Style

Naresh Bopparathi, Dr. P. Kalpana Devi. 2020. LOW POWER INPUT CLOCKED LATCH DESIGN BASED ON A SIGNAL FEED THROUGH USING FINFET TECHNOLOGY. Journal of Critical Reviews, 7 (19), 5593-5598. doi:10.31838/jcr.07.19.650



Chicago Style

Naresh Bopparathi, Dr. P. Kalpana Devi. "LOW POWER INPUT CLOCKED LATCH DESIGN BASED ON A SIGNAL FEED THROUGH USING FINFET TECHNOLOGY." Journal of Critical Reviews 7 (2020), 5593-5598. doi:10.31838/jcr.07.19.650



MLA (The Modern Language Association) Style

Naresh Bopparathi, Dr. P. Kalpana Devi. "LOW POWER INPUT CLOCKED LATCH DESIGN BASED ON A SIGNAL FEED THROUGH USING FINFET TECHNOLOGY." Journal of Critical Reviews 7.19 (2020), 5593-5598. Print. doi:10.31838/jcr.07.19.650



APA (American Psychological Association) Style

Naresh Bopparathi, Dr. P. Kalpana Devi (2020) LOW POWER INPUT CLOCKED LATCH DESIGN BASED ON A SIGNAL FEED THROUGH USING FINFET TECHNOLOGY. Journal of Critical Reviews, 7 (19), 5593-5598. doi:10.31838/jcr.07.19.650