Abstract

Filters are integral for the removal of various noise types, such as salt and pepper, Gaussian, and random noises, from images. Consequently, the hardware implementation of filters tailored for Very Large-Scale Integration (VLSI) assumes a pivotal role in real-time applications. Traditional hardware-based filters, however, grapple with challenges related to excessive look-up-table (LUT) usage, path delays, and power consumption. This research is centered on the implementation of a Median Filter (MF) utilizing Data Comparator (DC) logic. The approach commences with a multiplexer selection logic-driven data comparator, which identifies the high and low values from a pair of numbers. Subsequently, the data comparator is iteratively applied across nine-pixel combinations to determine the median value. Subjective and objective evaluations affirm that the proposed MF-DC outperforms existing approaches, exhibiting superior performance in terms of noise reduction and hardware metrics, including LUTs, delay, and power consumption.

Description