Abstract

This study focuses on the simulation and comparison of different dynamic logic circuits, followed by the proposal of a circuit to reduce power consumption. Through our investigation, we observed a significant reduction in power consumption and lower delays by employing the proposed buffer circuit. Furthermore, we explored the application of Gate Diffusion Input (GDI) techniques in the design of logic circuits. Specifically, we utilized GDI techniques to design logic circuits such as AND, OR, XOR, and multiplexers. Our findings revealed that this technique allows for the design of logic circuits with a reduced number of transistors. In addition, we addressed the design of a collector circuit using the GDI technique and presented a collector circuit implemented with this approach. Based on our analysis, we concluded that the proposed circuit exhibits considerably lower delay and power consumption compared to previous works. Overall, this study involves the simulation and comparison of various dynamic logic circuits, introduces a circuit for power consumption reduction, explores the utilization of GDI techniques in logic circuit design, and presents a collector circuit using this technique. Our results demonstrate the superior performance of the proposed circuit in terms of reduced delay and power consumption when compared to existing approaches

Description