Abstract

Resistive open defects in memory are gaining higher attention to the growing technology. With the advanced deep submicron technology, effects of change in temperature, supply voltage and process variation are stimulating to create numerous difficulties in the detection of the resistive open defect in memory. For assuring the reliable operation of the circuit, it becomes crucial that memory used in system-on-chip should be faulttolerant. This paper estimates the efficiency of the proposed Predischarged feeble cell detection technique used to detect open resistive defect faults in SRAM memory array. The fault detection capabilities are examined for a wide range of defect values at random locations in memory. The implementation of the proposed method gives less time latency and minimum area overhead of 7.74% for 2KB of memory.

Description